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Verification Engineer

Verification Engineer
by Admin on 04-19-2024 at 3:25 pm

Website CEVA

Description

Are you highly passionate with interest in Coverage driven verification, advanced interpretation to the UVM methodology while working in multi-platform verification environment?

Then you belong with us!

Here in CEVA, we are developing state of the art DSP ASIC projects in A.I, Vision, Wireless and Base-stations area. The VLSI verification team is responsible producing a fully verified IP with extra ordinary challenges, working on Functional, Formal and Emulation combined environment.

As part of this position you will be a part of the verification team, you will work on a full state of the art verification flow from architecture definition, through verification strategy, environment micro ARCH, test plan, functional coverage plan and up to advanced verification sign off process.

Requirements

  • B.Sc /M.Sc. graduates in Electrical Engineering from a leading University.
  • 2-6 years of experience in Verification.
  • Knowledge of SV-UVM, Specman and C++.
  • Self-motivated and self-directed, proactive.
  • Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization.
  • Ability to troubleshoot and analyze complex problems.
  • Great communication skills.
  • Team player.
Apply for job

To view the job application please visit www.ceva-ip.com.

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