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ASIC Synthesis/Timing Flow Engineer – Design Front End Implementation

ASIC Synthesis/Timing Flow Engineer – Design Front End Implementation
by Daniel Nenni on 08-15-2020 at 5:52 pm

Website TSMC

Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing constraint creation, analysis and closure
Requires proficiency with the design tools / flows tcl/perl development

Master Degree in Electrical Engineering or Computer Science with 4+ years ASIC implementation and tape-out experience.
The ideal candidate will have the following background:

At least 4+ year experience in ASIC design implementation related Synthesis, STA, Formality and flow development.
ASIC design flow and netlist flow checks – Synthesis, Design CDC, Logical Equivalence, Lint, SDC verification.
UPF flow for Synthesis and Low Power checks
Timing constraint creation from scratch and management
Self driven, highly motivated, organized, and schedule driven is a must
Familiar with EDA tools, Synopsys or Cadence and can integrate the flow with different stages of tools
Tcl/Perl programming languages are required
TSMC Technology is an Equal Opportunity Employer.

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