(Japan) APR/Physical Design Engineer or Manager

Description
Chip/Block level floorplan,
Clock tree synthesis,
Place & Route,
RC extraction,
STA, timing closure,
IR/EM analysis and fix,
DRC/LVS/ERC analysis and fix,
Tape-out sign off.
APR Flow development

Work location: Yokohama, Japan.

Qualifications
Requirements:

BCH degree and above in EE/CS
Minimum of 10+ years of working experience in digital design/design flow/APR chip implementation related field.
Experienced in advanced process nodes (28nm and below)
Familiar with Script languages (shell, python, TCL) or C/C++
Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology
Good customer-oriented attitude and communication skills
Good command of Japanese
English is a plus

Personal Attributes:

-Self-motivated in learning and problem-solving

-Good communication skill and a good team player

-Strong ownership and commitment

TSMC Technology is an Equal Opportunity Employer.