Front End Design & Automation Engineer

Responsibilities:
Working closely with Design and Technology partners in developing next generation DFT IP and flows for volume data collection and analysis.
Code and support flow and automation around Test IP implementation and DFT methodologies using Python/TCL/Perl.
Additional Responsibility (as needed)
Front-end ASIC development
Chip and block level RTL development, synthesis and verification
Formal verification and logical equivalency
Chip and block level Static Timing Analysis (STA) and ownership of constraints
Design verification using environments like UVM
May perform other duties as assigned including special projects and other administrative responsibilities.

Qualifications
Requirements:
M.S/B.S. in Electrical or Computer engineering
2+ years of hands-on experience developing Verilog/VHDL, System Verilog and driving through netlist  with commercial EDA tools for large, complex SOCs
Proven, hands-on tapeout and silicon bring up experience a plus
Knowledge/experience with ATPG / DFT tools and familiarity with IP test methods & implementation
Any mix of the following skills is a plus RTL design, Design Verification, Synthesis, &/or Static Timing
System level modeling a plus
Experienced timing analysis with Tempus/Primetime other commercial EDA tools
Must be able to work independently, collaborate with different teams and to be flexible to take dynamic and challenging assignments.
Must have good communication skills
Good understanding of chip and block level functional verification, specifying functional coverage using directed random and other test techniques

TSMC Technology is an Equal Opportunity Employer.