Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Analog &Mixed Signal Layout Design Engineer, II
In this role, you will be responsible for the resource and project planning and coordination for the analog layout design teams globally. You will be a go-to person for physical design team planning and multi-IP customer technical discussions. This role will involve close interaction and collaborative teamwork with multiple functional groups (front end, analog, ASIC, CAD) and the product teams globally. The ideal candidate will be an excellent communicator and comfortable managing multiple tasks.
You will be part of an advanced physical design team developing full custom analog and ASIC layout of high-speed integrated circuits. As an Analog/Mixed-Signal Layout, Project Engineer II you will be exposed to SerDes PHY design for PCIe, SATA, XAUI, and other protocols. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
Ideal background would include hands-on analog layout or ASIC physical design experience with project management background and aptitude.
Owns cross team planning, collaboration, and coordination ensuring that geographically distributed teams are well-aligned
Measure project and performance using appropriate systems, tools and techniques
Establish and maintain relationships with cross-functional teams, internal and external customers
Create and maintain comprehensive project documentation
Familiarity with physical design of analog and mixed signal CMOS circuits
Exposure and knowledge of the full design cycle from RTL to GDSII, including chip level
Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers
Solid organizational skills including attention to detail and multi-tasking skills
Autonomous, timely decision maker and able to cope with interrupts
Experience with advanced FinFET nodes, TSMC 16 nanometer and below
Exposure to SERDES design architectures, and layout
Experience with Design tool(s):
Custom Compiler, Cadence Virtuoso or equivalent
Verification tools: ICV, Calibre
Experience in working with Jira/Atlassian (or other such) tools
Strong working knowledge of MS Office Suite of applications
Preferred Experience and Requirements:MSEE or BSEE with a minimum of 2 years of related experience
Previous analog layout or ASIC physical design experience
Solid understanding of digital / mixed signal flows and SOC integration challenges
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact firstname.lastname@example.org.
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To view the job application please visit sjobs.brassring.com.