SemiWiki Podcast Banner

Senior Analog Design Engineer

Senior Analog Design Engineer
by Daniel Nenni on 08-08-2020 at 4:48 pm

Website Synopsys

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

Senior Analog Design Engineer

Does this sound like a good role for you?

In this role you will be responsible for reviewing SerDes standards and architecture documents to develop analog sub-block specifications, identifying and refining circuit implementations to achieve optimal power, area and performance targets, as well as proposing design and verification strategies that efficiently use simulator features to ensure highest quality design. The responsibilities include, and may not be limited to:
·       Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation,
·       Collaborating with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits,
·       Presenting simulation data for peer and customer review,
·       Mentoring and reviewing the progress of junior engineers,
·       Documenting design features and test plans,
·       Consulting on the electrical characterization of your circuit within the SerDes IP product.

Key Qualifications

·       PhD with 5+ years, or MSc with 8+ years of SerDes/High-Speed analog design experience.
·       In-depth familiarity with transistor level circuit design – sound CMOS design fundamentals.
·       Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes.
·       Detailed design experience with several of the following SerDes sub-circuits:
receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
·       Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
·       Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
·       Experience with EDA tools for schematic entry, physical layout, and design verification.
·       Knowledge of SPICE simulators and simulation methods.
·       Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
·       Experience with TCL, Perl, C, Python, MATLAB.

Share this post via: