Staff Verification Engineer

With offices around the world, Arm is a diverse community of dedicated and innovative engineers. By enabling an inclusive, meritocratic and open workplace where all our people can grow and succeed, we support our people to share their unique contributions to Arm’s success in the global marketplace.

Job Description

The System IP team has a track record of numerous successful deliveries, we have an open and relaxed culture where best-in-class, creative engineers work together on significant projects. Our upbeat and collaborative team builds System IP components used in future client, embedded and IoT devices.

At our design center, you will join a hardworking team. You will contribute to the verification planning, verification implementation, coverage closure, benchmarking, modelling of performant, energy efficient and secure IP components.

You will use novel technologies and methodologies to ensure the highest quality products as you collaborate with other Arm engineering teams to build complete IP solutions to address the performance, power and cost requirements for almost all application markets. Join and let’s invent the future together!

What will you do every single day?

• Perform SystemVerilog RTL verification and debug; formal bring-up of non-trivial IP blocks
• Develop verification plans, environments, determine the best approach to achieve required quality levels (SystemVerilog/UVM, Formal, scripting)
• Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional requirements, performance, power and area goals
• Propose and prototype new ways and define methodologies to reach goals more efficiently

Skills, experience, and qualifications

• Master’s degree in Electrical Engineering or Computer Engineering strongly preferred, Bachelor’s degree along with shown related experience may be substituted
• Minimum 2 years of post-degree work experience in RTL and microarchitecture design (think senior/staff types)

What significant contributions do we favor in your prior experience?

• Experience of block level RTL design and verification for non-trivial ASIC (or FPGA) developments; SystemVerilog preferred
• Familiarity with the Arm AMBA specifications or other bus protocols
• A solid understanding of digital design to include one or more from CPU, GPU and cache concepts, memory, I/O, etc.
• Exposure to all stages of the design cycle: initial concept, specification, implementation and testing, documentation, release and support
• Hands-on experience of formal verification techniques for rapid IP bring-up
• Object oriented software development, object-oriented design patterns
• Scripting, e.g. with Perl, Python, etc.
• Ability to travel occasionally for training and customer meetings
• Proficiency in both written and oral English