Staff/Sr. Engineer (Verification)
Website Achronix
Job Description/Responsibilities
The successful candidate will be responsible for the functional verification of high-performance digital logic for standalone and embedded FPGAs.
Responsibilities include the following:
- Define the test plan and setup the verification environment at unit and chip level
- Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL functionality
- Run functional simulations and regressions, including gate level and timing annotated simulations
- Debug issues, report and track bugs to closure
- Collect coverage metrics and track verification progress
- Support porting of the verification infrastructure for post-silicon validation
- Mentor junior engineers
Required Skills and Qualifications
- Experience designing/maintaining flows and methodologies from scratch
- Experience with digital VLSI design and verification
- Proficiency in Verilog coding and using a scripting language (e.g., Python or Perl) is a must
- Experience with Simulation, Debugging and Formal Verification
- Experience with UVM or System Verilog for verification is a plus
- Familiarity with using and/or designing FPGAs is a plus
- Familiarity with revision-control systems (e.g., perforce, git) is a plus
- Excellent debugging skills
- Well organized and excellent communication skills
- BS/MS in Electrical Engineering or Computer Science + 2-10 years’ experience
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