Staff/Sr. Engineer (Verification)

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix’s FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix’s products are supported by best-in-class EDA software tools.

Job Description/ResponsibilitiesThe successful candidate will be responsible for the functional verification of high-performance digital logic for standalone and embedded FPGAs.

Responsibilities include the following:

• Define the test plan and setup the verification environment at unit and chip level
• Write constrained-random and directed testcases in Verilog/System Verilog/UVM to verify RTL functionality
• Run functional simulations and regressions, including gate level and timing annotated simulations
• Debug issues, report and track bugs to closure
• Collect coverage metrics and track verification progress
• Support porting of the verification infrastructure for post-silicon validation
• Mentor junior engineers

Required Skills and Qualifications

• Experience designing/maintaining flows and methodologies from scratch
• Experience with digital VLSI design and verification
• Proficiency in Verilog coding and using a scripting language (e.g., Python or Perl) is a must
• Experience with Simulation, Debugging and Formal Verification
• Experience with UVM or System Verilog for verification is a plus
• Familiarity with using and/or designing FPGAs is a plus
• Familiarity with revision-control systems (e.g., perforce, git) is a plus
• Excellent debugging skills
• Well organized and excellent communication skills
• BS/MS in Electrical Engineering or Computer Science + 2-10 years’ experience