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Staff/Senior Hardware Engineer (RTL Design) – Core Technology

Staff/Senior Hardware Engineer (RTL Design) – Core Technology
by Admin on 05-17-2024 at 2:08 pm

Website Achronix

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. The Achronix FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All Achronix products are supported by best-in-class EDA software tools.

Job Description/Responsibilities

The successful candidate will be responsible for the development of high-performance digital logic used in standalone and embedded FPGAs. Primary focus is on designing and optimizing digital logic at the RTL level to meet functional and performance requirements.

  • Work closely with system architects and/or customers to understand system-level requirements and translate them into RTL specifications
  • Create and maintain design documentation, including specifications, test plans and design reviews
  • Develop RTL code using Verilog/SystemVerilog to describe the behavior of digital circuits
  • Optimize RTL code for area, power and performance while meeting design constraints
  • Conduct CDC, sanity and lint checks to verify overall consistency and integrity
  • Work with verification engineers to validate the design against functional and performance requirements, debug issues, report and track bugs to closure
  • Work with backend engineers to develop synthesis constraints and assist with timing closure
  • Assist in post-silicon bringup and validation
  • Mentor junior engineers

Required Skills

  • Experience designing and maintaining flows and methodologies from scratch
  • Familiarity with ASIC design flow, including synthesis, timing closure, linting and CDC verification
  • Proven experience in RTL design using Verilog/SystemVerilog
  • Strong understanding of digital design principles, data path, control path, and finite state machines
  • Proficiency in creating and using Makefiles
  • Familiarity with using and/or designing FPGAs is a plus
  • Familiarity with a scripting language (python or perl) is a plus
  • Familiarity with version control systems (e.g., perforce, git) is a plus
  • Excellent problem solving and debugging skills
  • Well organized with strong communication and teamwork skills

Education and Experience

  • BS/MS in Electrical Engineering or Computer Science + 2-10 years experience

The compensation range for this position is $120,000–$190,000. Salary ranges dependent on experience and location.

Apply for job

To view the job application please visit www.achronix.com.

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