Website Alphawave Semi
What you’ll need:
· Good understanding of overall design Flow RTL to GDS.
· Experience on signing off the full chip synthesis/STA for tape outs
· Hands on Experience on Both Block level and Full chip timing Constraints Development and Management for hierarchical designs.
· Thorough Understanding of DFT Constraints.
· Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools.
· good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing Convergence
· Must have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STA
· Must understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-off Must understand CTS/Other clock Distribution methodologies well.
· Good knowledge on Timing Budgets.
· Knowledge on Perl / TCL / Python scripting language
· Experience on multi voltage designs using CPF/UPF.
· Good understanding on timing/area/power/complexity tradeoffs on complex interface design
· Hands on experience on power analysis using PTPX
· Good understanding of VHDL / Verilog Constructs.
· Familiarity with IP level verification and strong RTL debugging capabilities is an added bonus
· Excellent problem-solving and analytical skills
· A self-motivated, enthusiastic team player who enjoys working with others
· Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form
What You’ll Do:
We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include
· STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs.
· Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes
· Timing analysis, and timing closure at Full chip level while supporting the PD team on Block/SS level timing convergence.
· Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts .
· Support Verification team to enable GLS.
· Drive the CTS strategies and provide feedback to Implementation Team.
· Drive and own the timing ECO generation and strategize the implementation methodology
· Develop Automation scripts with-in STA tools for Methodology development.
Apply for job
To view the job application please visit alphawave.wd10.myworkdayjobs.com.