Staff Digital Design Engineer

Summary

Innatera’s VLSI design team is responsible for design and realization of energy-efficient mixed-signal neuromorphic processors/SoCs for AI at the sensor edge. The team is looking for a Staff Digital Design Engineer.

We will trust you with:

• Designing and architecting digital IP and subsystems;
• Making sure the IP under test gets fully verified by the verification engineer;
• Designing and architecting the SoC level integrating all IP and subsystems;
• Aiding in verifying the SoC functionality with top-level tests;
• Assisting and/or performing all front-end design tasks: design, verification, DFT, synthesis, STA and formal equivalence checking.

Your experience includes:

• At least 10 years of experience in ASIC Design;
• Demonstrate ability to design from scratch complex digital modules, preferably in the area of hw accelerators, Computer Vision, DSP or Neural Netwoks;
• Deep understanding of the SW-HW systems;
• Power aware design and understanding of power domains;
• Experience in architecting complex SOC subsystems or even entire SOCs;
• Strong documentation skills;
• Demonstrate the ability to work within a team with minimum supervision;
• Design or integration of RISC/DSP processors and their ecosystem;
• Strong verification skills with impeccable reuse and best practices;
• Experience with various fast&slow communication protocols (SPI, I2C, UART, …) and on-chip bus protocols (AMBA, OBI, …);
• Test methodologies (using JTAG, scan, memory BIST);
• EDA tool flows and scripting (eg: in Python).
• Version control (git) and CI/CD (github, gitlab, Jenkins, …);
• (Embedded) C and/or C++ and/or System C;
• Synthesis, timing analysis and timing closure;
• Chip bring-up, silicon and system debug.

Does it sound interesting – then apply by the link below!