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Staff DFT Engineer

Staff DFT Engineer
by Admin on 12-14-2023 at 3:28 pm

Website Alphawave Semi

What You’ll Do

  • To work with multiple HSIO IPs (CXL/PCIe, DDR, HBM, UCIe, etc.) and SoC designs
  • Design and implement state-of-the-art DFT architecture to meet growing industry demands for efficient test and debug capabilities.
  • Generate and Insert DFT structures at the RTL and gate level and verify the correct operation of those structures from RTL to back annotated gates.
  • Generate scan-inserted netlists, produce ATPG patterns to achieve coverage targets and simulate them for correctness.
  • Run timing analysis, review constraints and waivers, analyze violations and work with other teams to fix the design.
  • Produce ATE test patterns for MBIST, Scan, Functional & analog testing and support silico ATE testing and debugging.
  • Participate in diagnostics and failure analysis for customer returns.
  • Mentor and lead a team of junior engineers to accomplish all the above tasks within the defined project constraints.

What You’ll Need:

  • Bachelor’s degree in engineering science, Electrical and Computer Engineering or Computer Science .
  • 5+ years of experience in the semiconductor industry in engineering or leadership roles in RTL, Verification, DFT or FE/PD capacity. Applicants with less experience may be considered for other DFT positions within the team.
  • Experience with various DFT EDA tools from Tessent, SNPS and Cadence.
  • Experience with UNIX, Perl, TCL and other scripting languages is a must.
  • RTL and/or VHDL coding experience is a plus
  • Design verification experience is a plus.
  • VCS/NCSim or Verilog simulator experience. Familiarity with Spyglass tool & checks.
  • Familiarity with DesignCompiler/DFT Compiler/TestKompress/Tessent tools/TetraMax.
  • Experience with Tessent MBIST or SNPS SMS compilers.
  • Experience with static timing analysis and PrimeTime tool.
  • Understanding and experience with modern DFT techniques, JTAG standards (1149/1500/1687), scan and clock control designs and best practices for ATPG.
  • Understanding of general high-speed, small-tech node design techniques

“Hybrid work environment”

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

  • Great compensation package
  • Health Insurance
  • Retirement Savings
  • Paid time off
Apply for job

To view the job application please visit

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