Staff ASIC Physical Design Engineer

The “R&D Professional” team has broad understanding in mixed-signal design, implementation, firmware and verification. The team has experience in both back-end and front-end ASIC development flows with a mandate to provide targeted support to mixed-signal High-Bandwidth Memory (HBM) and DDR PHY IP customers. We are looking for a candidate to join the team to help with back-end tasks. The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus:

• ATPG/DFT
• Static Timing Analysis and timing budgeting
• Synthesis
• Lint/CDC
• Place and Route

The diversity of tasks allow each team member to develop new skills and learn about all aspects of our PHY design. The main focus of the team is to support the application engineers solving customer problems, usually requiring deep investigations into the design. When not working on customer questions we use our knowledge to drive product improvements. Experience with HBM or DDR protocols is a definite asset but not mandatory. Your tasks will be adapted to your skills and development and will include some or all listed below,

• Interact with and, in some instances, visit customers
• Provide guidance to customers on PHY implementation tasks
• Participate in the generation of data books, application notes, and white papers
• Perform constraint development and physical design activities
• Other related duties as assigned by the manager

Key Qualifications

• BSEE degree or Applied Science degree (or equivalent) with 2+ years of related experience
• Excellent communication and presentation skills