Sr. Physical Design Engineer
Website Flex Logix
Flex Logix is the leading provider of reconfigurable computing technology for both AI inference and eFPGA IP solutions. Our offerings push the leading edge of hardware, software and system design; pioneering new approaches to important problems.
- Our InferX X1 is the industry’s most-efficient AI edge inference accelerator that brings AI to the masses in high-volume applications by providing a new silicon efficient dynamic logic paradigm for inference processing. InferX achieves GPU-level inference performance with a fraction of the die area and memory footprint.
- Our EFLX embedded FPGA (eFPGA) IP enables any SOC design to flexibly handle changing protocols, standards, algorithms, and customer requirements and enables reconfigurable accelerators that speeds key workloads up to 1000x compared to a general purpose processor. EFLX eFPGA is available in a wide range of process technologies and supports designs ranging from low cost microcontrollers to 5G baseband processing solutions.
Flex Logix is looking for Physical Design Engineers to join our growing team.
Responsibilities
- Generate block level static timing constraints.
- Build IP floor-plan including pin placement, partitions and power grid.
- Develop and validate high performance low power clock network guidelines.
- Perform block level place and route and close the design to meet timing, area and power constraints.
- Generate and Implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
- Participate in establishing CAD and physical design methodologies for correct construction designs.
Required Experience
- Bachelors or Master’s Degree in EE/CS required.
- 5+ years of Physical Design experience on IP and/or SOC designs.
- Experience in developing and implementing Power-grid and Clock specifications.
- Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, floor-planning, and place & route.
- Deep understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.
- Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
- Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
- Knowledge of Basic HDL languages like Verilog to be able to work with logic design teams for timing fixes.
Preferred Experience
- Familiar with power intent definition, implementation and verification flows.
- Familiar with power analysis and optimization methods.
- Power user of industry standard Physical Design & Synthesis tools.
We are looking for passionate team members, to be part of an aggressive, venture-backed startup team that is changing chip architecture. Must be entrepreneurial, innovative problem solver, willing to work hard and have fun.
As we continue to grow and expand our company, we are hiring for all office locations. You must live near one of our main offices located in: Mountain View (CA), Austin (TX), Chicago (IL) or Vancouver (BC). We offer a flexible work schedule.
You must have US citizenship or permanent residency (“green card”) or hold a current H1-B visa to work in United States.
Flex Logix recruits, employs, trains, compensates and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.
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