Sr. Mask Designer

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix’s FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix’s products are supported by best-in-class EDA software tools.

Job Description/ResponsibilitiesAs a member of the Achronix layout team, the successful candidate will be responsible for the delivery of clean layouts which involves the creation of custom digital layouts for macro, block and TILE libraries; including running a complete set of design verification checks.

Primary Job Responsibilities

• Review and analyze floorplans for complex circuits with circuit designers
• Interpret and resolve DRC, ERC, LVS, BEOL and ANTENNA reports for sign-off
• Debug netlists and/or schematics

Secondary Job Responsibilities

• Send Design Reviews to the design team for final review and sign-off
• Prove ETAs for the completion of layouts
• Provide weekly reports

Required SkillsGeneral:

• High-level proficiency in layout floorplans for standard cell and hierarchical layout assembly
• Fully knowledgeable of DRMs for the creation of layouts at 5nm, 7nm and 12/16nm.
• Proven experience accomplishing assignments with high quality, minimal supervision and on-time delivery
• Good understanding of issues related to RC delay, EM/IR and coupling capacitance
• Expert user of Advanced CAD layout tools; Custom Compiler or Virtuoso
• Excellent verbal and written communication skills, and able to work with multi-functional teams

Layout Platforms:

• Expert user of Custom Compiler or Virtuoso, specifically using SDL (Schematic Driven Layout) flow related to connectivity, schematics, generating pins and resolving mismatches
• Fast learner of Advanced CAD tools for acceleration of layouts

Verification:

• Expert user of IC Validator or Calibre for running DRC, LVS, ANTENNA and DENSITY checks, including debugging and interpretation of design rules and reports
• Debugging of log files related to ICV failures

Analytical Skills:

• Strong engineering problem solving and analytical skills
• Debugging of verification log files

UNIX/LINUX/Windows:

• Experience with UNIX/LINUX is a must
• Experience with MS Windows and web-based tools

Experience

• Minimum of 5 yrs. experience in working with finFet technologies
• Experience user of CAD tools, specifically related to schematic-driven-layouts
• Proven experience as a self-starter; able to complete assignments with minimum supervision

Education and Experience

• BS Degree or equivalent