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Sr. Manager/Principal DFT Engineer

Sr. Manager/Principal DFT Engineer
by Admin on 12-14-2023 at 3:29 pm

Website Alphawave Semi

What you’ll Do

  • Acting as a senior member of Alphawave central DFT methodology group responsible for developing, maintaining and supporting flows across all company business units and projects
  • Architecting methodologies and flows for an integrated, RTL centric “shift left” DFT environment across company IPs, chiplets and SoC designs.
  • Developing automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
  • Building IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
  • Writing static timing constraints, creating waivers and devising flows for bullet proof timing checks
  • Hiring, training and leading DFT engineers in day-to-day tasks and activities to fulfill company road map.

What You’ll Need:

  • Bachelor’s degree in engineering science, Electrical and Computer Engineering or Computer Science
  • 10+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
  • Vast experience to various DFT EDA tools from Tessent, SNPS and Cadence
  • Good knowledge and understanding in Verilog/VHDL and SystemVerilog
  • Exposure with CAD and automation. Good exposure for using de-Perl techniques in creating generic codes. Knowledge of TCL and Python is a plus.
  • Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
  • Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs is highly desirable.
  • Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.
  • Experience in core wrapping, pattern retargeting & packetizing ATPG techniques. SSN knowledge is a plus.
  • Experience in scripting/reviewing SCAN/MBIST timing constraints.
  • Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions.

“Hybrid work environment”

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

  • Great Compensation Package
  • Health Insurance
  • Retirement Savings
  • Paid Time Off
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To view the job application please visit alphawave.wd10.myworkdayjobs.com.

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