Sr Design Engineering Manager

Hiring Requirements

The position requires managing and leading a high-speed serial link mixed-signal circuit design team in IPG group in Cadence Bangalore. The position demands 15+ years of experience in relevant technologies and proven leadership in managing a high-performing team for delivering industry-leading products for advanced nodes. Strong communication and inter-personal skills are a must.

Job Details

• High-speed PHYs for emerging protocols/products – .e.g. Ethernet 112G/56G/25G/10G
• Thorough understanding of custom circuit design tools and flows in deep sub-micron CMOS;  expertise/exposure in Cadence tools/flows is a must (e.g. Virtuoso)
• Chip planning and block implementation
• Strong project management skills to drive efficiency/execution across cross-functional groups
• The position requires leadership qualities in a dynamic, learning and agile environment with opportunity for career growth and significant business impact.