Sr Design Engineering Manager

Coordinate and oversee Bangalore staff doing test chip bringup and validation, customer bringups and support, as well as collateral development of IBIS, Die models, SIPI analysis, test software development.

Track and drive Jira ticket closure by staff.

Plan customer silicon bringups and post silicon queries of our IP and help drive team working to debug customer issues with same.

Recommend and pursue improvements to ensure the highest quality IP is produced by Cadence and minimize any silicon issues experienced by our customers.

Position Requirements

• Candidate’s background should include a minimum 5 years of technical experience, preferably in the area of SERDES, DDR or other high-speed interfaces
• Ability to Communicate with global teams (US, India, China, EU), which work in different time-zones
• People management skills.   Experience or demonstrated readiness to manage a high performance team
• Excellent problem-solving skills, good communication skills and ability to work cooperatively in a team environment
• Organizational skills to track and drive team efforts
• Work with design team
• Mentor Junior Engineers
• BEng, MEng