Sr Application Engineer, SVG

Qualification Requirements

• • Bachelor’s degree in Computer Science, Electrical/Electronic Engineering, or related field
  • Has the knowledge and desire to take on new challenges

Experiences/Skills

• • At least 3 years’ experience in HDL design and verification
  • Experience in using EDA tools (mainly functional simulators and debuggers)
  • Experience in evaluating EDA tools
  • Knowledge of AMBA, bus interconnect and software are better
  • Programming skills to efficiently perform tasks (practical experience in shell scripting, C/C++, Perl, Tcl, Python, Ruby, etc.)
  • Experience in construction of verification environments or functional verification using verification languages(HDL/SystemVerilog/e/SystemC) or verification methodologies (UVM, etc.)
  • Can provide optimal solutions to the verification tasks that customers have and can continue to build good trust with customers
  • Can communicate in English (email exchange and technical discussion)
  • Ability to solve problems; can work independently with high motivation
  • Does not put restrictions on scope of work, engages in everything with a passion, and can grow while absorbing new technologies

Job Description

• • Technical pre-sales and post-sales services for customers of Cadence’s functional verification products