Solutions Engineer, Staff

Job Description and Requirements

Looking for innovative, out of the box thinking Solution Engineers to be a part of the Solution Team under the Hardware Analytics & Test(HAT) Group. Synopsys technology is at the heart of innovations that are changing the way we live and work. The HAT Group is a critical part of the change delivering a complete Test & Silicon Lifecycle Management (SLM) solution to fulfill the customer needs.

The Solutions engineer will be working on the High Speed IO solution for Test. The Solution Engineer would be accountable for FPGA prototyping, through validation of the various features & capabilities. The Solution Engineer will interact with the customers to enable the High speed IO solution in their designs, take part in the exploration phase and architectural conversations. The Solution Engineer provides technical help to ensure customer success and satisfaction. Become experienced in the High Speed IO solution, setup regression cases and win new customers through product demonstrations, evaluations, and benchmarking. They must be able to interact effectively with customers and internal development teams. The role would also involve prototyping new methodologies, review gathered data, identify the viability of technology and present the findings.

Responsibilities include but not limited to the following:

• FPGA Protoyping of the High Speed IO Solution on various FPGA boards.
• Validation of the High Speed Solution on multiple design Architectures.
• Packetization of STIL pattern to protocol based patterns.
• Building and maintaining regression suits.
• Participate in customer architecture reviews and help them through implementations.
• Ability to multitask across many issues and priorities.
• Desire to help customers exploit new technologies are essential for success in the position

Qualification

• Minimum of BS + 10 years of relevant experience/MS +8 years in Electrical Engineering or Computer Engineering or other relevant field of study.
• Good knowledge of Digital Design and Timing.
• Experience with RTL Coding, Verification.
• Experience with Verilog and any scripting language
• Good knowledge of USB, PCIe and other types of high speed interfaces and the functional protocols.
• Good knowledge of the various Network on Chips (NoC), specifically AXI.
• Experienced in implementing designs in various types of FPGA – Xilinx, Altera, HAPS boards.
• Excellent communication and soft skills