- Independently work on the verification of ASIC function blocks in terms of Verification Plan, Build Test bench, Develop Test cases, Simulation & Debug.
- Setup IP/chip level verification env, modeling.
- RTL/Gate-level simulation/regression. Code/function coverage analysis and closure
- Master/PhD degree in EE/CS related specialties, work experience and rank are not limited.
- Familiar with design and verification languages (Verilog, SystemVerilog, SVA etc.).
- Relevant digital design experiences (on FPGA or ASIC, including course projects).
- Familiar with C/C++, perl, python etc.
- Knowledge of computer architecture (ARM or RISC-V) & on chip bus AMBA/NOC is a plus.
- Knowledge of Audio Video interfaces: MIPI/HDMI/DP/SPDIF/I2S etc. is a plus.
- Knowledge of interfaces USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN etc. is a plus.
- Knowledge of AI or Video Codec is a plus.
- Self-motivated, team work, and good communication skills in Chinese and English.
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To view the job application please visit www.verisilicon.com.