- Contribute and work on the chip and sub-blocks in terms of synthesize, timing optimization and sign-off.
- Contribute and work on the chip and sub-blocks in terms of Design PPA.
- Contribute and work on the chip and sub-blocks in terms of SDC writing change and hand-off.
- Contribute and work on the chip and sub-blocks in terms of DFT coverage analysis.
- Design test logic, insert Scan chain, MBIST, Boundary Scan circuits, finish DFT patterns generation and simulation.
- Work closely with physical implementation engineers, to solve floorplan, timing analysis, optimization / closure.
- Master’s or above degree in EE/CS related majors, working experience is unlimited.
- Programming skills in Verilog HDL and System Verilog.
- Familiar with EDA tool, Such as Synopsys VCS 、 Verdi, Cadence IUS, Mentor QuestaSim etc.
- Knowledge of SoC design techniques is a plus.
- Knowledge of physical implementation techniques is a plus.
- Knowledge of low-power design or DFT design techniques is a plus.
- Familiar with DDR, PCIe, USB, MIPI, etc.
- Familiar with high-speed interface techniques is a plus.
- Knowledge of FPGA timing constraints and timing closure background is a plus.
- Familiar with linux OS, programming skills in Shell/Perl/Python/TCL scripts is a plus.
- Self-motivated and a good team player. Good communication skills in both Chinese and English in either listening, speaking, reading or writing.
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To view the job application please visit www.verisilicon.com.