SoC FE Flow Engineer
Descriptions
- Capable of contributing to and working on the chip and sub-blocks in terms of synthesize, timing optimization and sign-off.
- Capable of contributing to and working on the chip and sub-blocks in terms of Design PPA.
- Capable of contributing to and working on the chip and sub-blocks in terms of SDC writing change and hand-off.
- Capable of contributing to and working on the chip and sub-blocks in terms of DFT coverage analysis.
- Design test logic, insert Scan chain, MBIST, Boundary Scan circuits, finish DFT patterns generation and simulation.
- Work closely with physical implementation engineers, to solve floorplan, timing analysis, optimization/closure.
Requirements
- Master/PhD degree in EE/CS related specialties,work experience and rank are not limited.
- Course knowledge and project experience in the related areas.
- Programming skills in Verilog HDL and System Verilog.
- Familiar with EDA tool, Such as Synopsys VCS、Verdi, Cadence IUS, Mentor QuestaSim.
- Knowledge of SoC design techniques is a plus.
- Knowledge of physical implementation techniques is a plus.
- Knowledge of low-power design or DFT design techniques is a plus.
- Familiar with DDR, PCIE, USB, MIPI, etc high-speed interface techniques is a plus.
- Knowledge of FPGA timing constraints and timing closure background is a plus.
- Familiar with Linux OS, programming skills in Shell/Perl/Python/TCL scripts is a plus.
- Self motivated, team work, and good communication are a must.
ASML- Soft revenues & Orders – But…China 49% – Memory Improving