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SoC Design Verification Engineer

SoC Design Verification Engineer
by Admin on 07-08-2022 at 2:02 pm

Website Alphawave

What You’ll Do 

  • Work closely with the SoC architect, RTL designers and other verification engineers to achieve verification closure
  • Be responsible for functional verification of a block
  • Develop and execute test and coverage plans to ensure the functional completeness
  • Create, reuse and debug testbenches, verification components and tests for verification of the design
  • Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

What You’ll Need

  • Minimum 3+ years of verification experience on large ASIC development projects
  • Solid understanding of Computer Architecture and Digital Design concepts
  • Strong background in Verilog, System Verilog, C/C++/OOO coding techniques
  • Experience working with UVM, OVM or equivalent
  • Knowledge of PCIe/Ethernet protocol is an added advantage
  • Experience with constrained random verification, functional coverage and assertions
  • Familiarity with scripting languages: perl/tcl /Bash/python
  • Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent
  • Strong analytical skills and attention to detail
  • Bachelor’s (or preferably Master’s) degree in Computer Engineering, Computer Science, Electrical Engineering or similar

About You

  • Excellent communication skills
  • Able to listen to and appreciate ideas and opinions that differ from yours
  • Extremely detail oriented
  • Superb analytical and problem-solving skills
  • Drives for consistency
  • Takes personal pride in high standard of outputs
  • Self-motivated and self-managing
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