- Independently work on the design of ASIC function blocks in terms of Design Spec, Architecture definition, block design, RTL coding, logic synthesis and timing analysis (STA).
- Cooperation with verification engineer, finish verification job and responsible for design quality. Review verification plan, Simulation & Debug, cdc check.
- As SoC owner, work closely with system engineers, physical implementation designers, and testing engineers to do functional verification, floorplan, timing optimization/closure and DFT& ATE testing consideration.
- Master/PhD degree in EE/CS related specialties, work experience and rank are not limited.
- Mastery of EDA tools(Synopsys or Cadence, VCS, Xcelium, DC, PT etc.) and capability of solving technical issues as below is a must: Design specification, RTL coding and style critique, block design, chip-level integration; logic synthesize and timing analyze (STA);System C modeling, System Verilog based on UVM methodology.
- Relevant digital design experiences (on FPGA or ASIC, including course projects).
- Familiar with C/C++, perl, python etc.
- Knowledge of computer architecture (ARM or RISC-V) & on chip bus AMBA/NOC is a plus.
- Knowledge of Audio Video interfaces: MIPI/HDMI/DP/SPDIF/I2S etc. is a plus.
- Knowledge of interfaces USB/PCIe/Ethernet/DDR/SD/eMMC/SPI/CAN etc. is a plus.
- Knowledge of AI or Video Codec is a plus.
- Self-motivated, team work, and good communication skills in Chinese and English.
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