Verification Engineer

Responsibilities

Understand CPU and SoC designs from an architectural level and create effective verification strategies for these designs.

Create test plans and test environments.

Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.

Develop checkers and assertions to verify the design.

Write functional coverage, analyze both code and functional coverage, and close coverage holes.
Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.).

Solid understanding of CPU and SoC architectures, or a strong desire and ability to learn same.

A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).

Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
Excellent debug skills.

Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).