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RTL Design Engineer – Power Management

RTL Design Engineer – Power Management
by Daniel Nenni on 07-05-2020 at 11:03 am

  • Full Time
  • Sam Mateo, CA
  • Applications have closed

Website SiFive SiFive

As a Power Management/Reset/Clock Microarchitect/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU core, subsystem and SoC IP based on the revolutionary open RISC-V and TileLink architectures.

You will create power management, reset, and clocking solutions that provide the central nervous system for cutting-edge RISC-V CPU and SoC IP designs. You will work in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance – delivering hardware at the speed of software!

LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.

Responsibilities

Work with architecture team to understand and define power management requirements.

Architect, design and implement core clocking, reset and power management solutions.

Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.

Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.

Work with software team to enable and optimize power management features.
Requirements

7+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.

Experience in high-performance, energy-efficient CPU and SoC designs.

Expertise in CPU and SoC clocking, reset design, and power management, including:

Reset control and design strategies;

Clock generation, dynamic clocking, clock gating, and clock boundary crossing strategies;

Power state definition and management and Power Management Unit (PMU) design;

Dynamic and static power management techniques, including retention and power-up/down sequencing;

Dynamic voltage and frequency scaling (DVFS) and Di/dt mitigation strategies; and
Power-aware verification.

Understanding of DFT and MBIST, Debug and Error handling in CPU designs.

Proficiency with hardware (RTL) design in Verilog, System Verilog, or VDHL.

Experience with Scala and/or Chisel is a plus.
Attention to detail and a focus on high-quality design.

Ability to work well with others and a belief that engineering is a team sport.

Knowledge of at least one object-oriented and/or functional programming language.

Background of successful CPU or SoC development from architecture through tapeout.

BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

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