Lead Verification Engineer

Responsibilities

Architect test methodologies applicable to a wide range of CPU and SoC designs.

Understand CPU and SoC designs from an architectural level and create effective verification strategies for these designs.

Build test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.

Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.

Provide technical leadership for verification engineers and coordinate technical teams to execute our verification strategies to meet program goals.

Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

10+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.), especially in hands-on testbench development and test suite generation.
Prior verification technical leadership required and some management experience is a plus.
Solid understanding of and experience with verification of CPU and SoC architectures.
A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).
Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).