Work closely with pre-sales teams to provide ASIC IP solutions to the customer.
Work very closely with IP Vendors and customers in defining, qualifying and procuring new custom and existing digital blocks.
Qualification and integration of several types of standard cells, memories, I/O’s and digital cores in SoCs.
Provide product and technical support to other engineering teams.
2+ years of experience in IP /Library Design (standard cells, memories, I/O’s, Analog Blocks, etc) / Application Engineering.
Experience with Front-end or Back-end (Including HSPICE) tools from Cadence, Synopsys and Mentor.
Experience in analog/mixed signal designs and /or DDRX PHYs/SerDes.
Good understanding of IP design, ASIC Design Flow and integration related issues.
Excellent verbal and written communication skills.
Proficient in writing scripts for automation.
Bachelor’s degree or equivalent in Electronics Engineering, Computer Science, or closely related field. MSEE is preferred but not required.