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RTL Design Engineer – RISC-V CPU

RTL Design Engineer – RISC-V CPU
by Daniel Nenni on 09-12-2020 at 6:14 pm

Website SiFive SiFive

Responsibilities

Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.

Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.

Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.

Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.

Requirements

2+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.
Experience with designing an out-of-order system ( high-performance DDR controller or caches controllers on a multicore system.)
Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; integer; floating-point, and vector units; load-store unit; cache and memory subsystems.
Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
Knowledge of at least one object-oriented and/or functional programming language.
BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.
Knowledge of RISC-V architecture is a plus.
Experience with Scala and/or Chisel is a plus.
Attention to detail and a focus on high-quality design.

Ability to work well with others and a belief that engineering is a team sport.

Apply for job

To view the job application please visit www.sifive.com.