Design Verification Engineer

Responsibilities

Review and influence product definition and specifications from a verification perspective
Architect and design debug and verification hooks as needed

Select the best tools and methods for verification
Help to prioritize the verification work efforts
Brainstorm and drive solutions across disciplines to improve product quality and engineering productivity

Requirements

A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.)

Familiarity with and/or ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)

A conscientious and thorough approach to Design Verification

Solid understanding of processor and SoC architecture, or a strong desire and ability to learn same

A passion for verification as a long term career path

Good interpersonal skills to listen to diverse points of view and influence people from different disciplines

An unwavering commitment to product quality