Physical Design Engineer

Responsibilities

Implement and optimize our broad portfolio of RISC-V CPU’s from RTL to GDSII.

Close aggressive performance, power, and area (PPA) goals at block and/or CPU level.

Collaborate with the microarchitecture and RTL teams to optimize PPA trade off’s.

Contribute to physical implementation flow development to drive best in class automation and PPA.

Requirements

8+ years of physical implementation experience with multiple tape outs in a wide range of technologies (45nm – 5nm); Experience with CPU implementation and advanced process nodes (16nm and below) is preferred.

Expertise in synthesis, DFT insertion, floorplanning, place and route, clock tree synthesis, static timing, power analysis, and signal and power integrity.

Experience with physical signoff (DRC/ANT/LVS/DFM, etc.) and engineering change orders (ECO’s).

Knowledge and skill in optimizing PPA through floorplanning, placement and timing constraints, useful skew, and similar techniques.

TCL scripting; Python scripting is a plus.
Attention to detail and a focus on high-quality design.

Ability to work well with others and a belief that engineering is a team sport.