RTL Design Engineer – Power Management

Responsibilities

Work with architecture team to understand and define power management requirements.

Architect, design and implement core clocking, reset and power management solutions.

Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.

Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.

Work with software team to enable and optimize power management features.

Requirements

7+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.

Experience in high-performance, energy-efficient CPU and SoC designs.

Expertise in CPU and SoC clocking, reset design, and power management, including:
Reset control and design strategies;
Clock generation, dynamic clocking, clock gating, and clock boundary crossing strategies;
Power state definition and management and Power Management Unit (PMU) design;
Dynamic and static power management techniques, including retention and power-up/down sequencing;
Dynamic voltage and frequency scaling (DVFS) and Di/dt mitigation strategies; and
Power-aware verification.

Understanding of DFT and MBIST, Debug and Error handling in CPU designs.

Proficiency with hardware (RTL) design in Verilog, System Verilog, or VDHL.

Experience with Scala and/or Chisel is a plus.
Attention to detail and a focus on high-quality design.

Ability to work well with others and a belief that engineering is a team sport.

Knowledge of at least one object-oriented and/or functional programming language.

Background of successful CPU or SoC development from architecture through tapeout.

BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.