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Senior Verification Engineer – Digital , DesignWare IP

Senior Verification Engineer – Digital , DesignWare IP
by Daniel Nenni on 07-04-2020 at 5:34 pm

Website Synopsys

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

ASIC Digital Verification Engineer

We’re looking for an ASIC Digital Verification Engineer to join the team. Does this sound like a good role for you?

This role involves developing and work on VLSI IP verification of controllers related to complex protocols.  Additionally, you’d:

  • Create design and verification specifications
  • Determine test bench design, and test cases
  • Define module interfaces and formats
  • Generate documentation for circuit development, test plans, verification environments, and usage.

Digital  ASIC Verification engineer to work on VLSI IP verification of controllers related to complex protocols.  The candidate will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Senior Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain.

Responsibilities include but not limited to the following:

  • Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/Ethernet/ USB/ MIPI
  • Be an individual contributor in the Verification Tasks – Architect testbenches, coding of TE, debug, verification coverage improvement, etc.
  • Will contribute to technical review of TE Code of small and medium complexity.
  • Will contribute to technical process and quality improvement to achieve high quality deliveries
  • Will be expected to Solve complex/ abstract problems
  • The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment.
  • The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
  • May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers.
  • The role offers ample scope to mentor junior engineers and interns and to enhance ones’ leadership skills.

Key Qualification:
BE +8 years of relevant experience / MTech+7 years of relevant experience in Electrical Engineering or Computer Engineering or other relevant field of study.

Preferred Experience:
6 years of relevant experience in:

  • Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc.
  • Knowledge of one or more of protocols: AMBA (AMBA2, AXI, CHI)/ SD/eMMC/ Ethernet/USB/ DDR/PCIe MIPI
  • Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM/ VMM/OVM.
  • Test Planning, Coverage Planning, Assertion Planning
  • Hands on experience with System Verilog/ VERA/ Specman coding and Simulation tools; Knowledge of C++/ OOPs Concepts
  • Experience with Perforce or similar revision control environment
  • Knowledge of Perl/Shell scripts.
  • Exposure to quality processes in the context of IP design and verification is an added advantage
  • Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.
  • In addition, the candidate should have good communication skills, will be a team player and will have good problem-solving skills.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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To view the job application please visit sjobs.brassring.com.