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Senior Verification Engineer

Senior Verification Engineer
by Admin on 02-07-2023 at 8:06 pm

  • Full Time
  • UK

Website Veriest


This position includes hands-on SOC verification tests development for full chip, cluster, and block levels.

Planning and implementation of verification environments using automated tools – mainly System Verilog.


  • B.Sc. in Electrical or Computer Engineering or Computer Science.
  • Minimum 5 years of experience in SoC Verification.
  • Knowledge and experience in System Verilog or ‘e’ (Specman) languages.
  • Vast knowledge of verification flow (block level & full chip verification).
  • Familiarity with verification environments: VMM, OVM, UVM – an advantage. 
Apply for job

To view the job application please visit www.veriests.com.

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