800x100 static WP 3 (2)

Senior Verification Engineer

Senior Verification Engineer
by Admin on 03-12-2024 at 4:01 pm

Website Synopsys

In this position you will be responsible to define and implement test plan based on UVM. You will work across teams and/or different time zones and be proactive to improve testbench features with basic guidance.

We’re looking for someone with strong debug capabilities to isolate and detect RTL/TB bugs providing a solution for most of the cases. Good communication skills will help to influence larger team members creating a technical development path according to their own professional development and personal goals.

Multitasking is required and be able to manage their own assignations based on priorities.

Responsibilities:

  • Strong understanding of verification process and flow.
    • Join a project at any phase with minimal disruption.
    • Participate as a lead and/or contributor.
    • Quickly adapt to a variety of different environments, methods, and standards.
  • Ability to create a high-level verification plan.
    • Derivation of verification requirements from design requirements
    • Derivation of project schedule from verification requirements
    • Architect complex test environments.
    • Identification and integration of re-use
  • Ability to create a complex constrained random test environment.
    • Setup, build and run test-benches.
    • Develop agents for complex interfaces (protocol/retries/split transactions)
    • Application of direct and random methods
    • Application of coverage analysis (types and convergence methods)
    • Analyzing and debugging failures to establish root-cause.
  • Strong understanding of Object-Oriented Programming (classes, methods, polymorphism)

Requirements:

  • Bachelor’s degree in electrical engineering, Computer Engineering, or Computer Science with 3+ years of experience in the verification of ASIC/FPGA devices.
  • Minimum 3 years of experience in UVM Methodology based verification.
  • Excellent knowledge of SystemVerilog hdl.
  • Emulation experience is a plus.
  • Highly skilled with industry standard simulation Synopsys VCS.
  • Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
  • Strong algorithmic and problem-solving skills.
  • Good knowledge of scripting languages such as perl, phyton, ruby.
  • Strong understanding of standard protocols (DDR4, GDDR, HBM, AMBA will be great)
  • Comfortable and confident interacting with customers.
  • Excellent written and verbal communication skills.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Apply for job

To view the job application please visit careers.synopsys.com.

Share this post via: