Senior/Staff Software Engineer

Arm Artisan Logic/GPIO products deliver optimized performance, power and area results and are widely used in designs ranging from performance critical to cost sensitive and low power applications.

We are looking for a Staff Software Engineer to develop and implement CAD software solution for Logic/IO physical IP development and validation flows.

This is an excellent opportunity to join a passionate and highly motivated team and design/implement sophisticated software solution for powerful Arm physical IP products.

What will I be accountable for?

• Design & develop efficient, scalable & massively parallel system to run EDA workloads on premise and/or Cloud
• Use innovative software design skills to integrate and deploy complicated methodologies and EDA tools for Logic/IO physical IP production and delivery
• Working with circuit designers and third-party EDA vendors to develop/deploy/support logic/IO CAD software solutions
• Leading Work-Package/Point-Tools development (requirement, specification, development, testing, documentation)

Job Requirements

What skills, experience and qualifications do I need?

• Bachelor / Masters Engineering degree in Computer Science / Information Science / Electronics and Communication or other related technical fields.
• 4+ Years of expereince
• Proficient in at least one of the programming languages: Java, C++ (OOPS based)
• Good scripting skills (Perl, Shell or TCL) in Linux/Unix environment
• Good experience in CAD/EDA software development
• Good software architecture know-how, excellent coding, software testing techniques and debugging practices
• Good communication skill and a team-player
• Eager to explore new technologies, autonomous and willing to share knowledge
• Desirable Skills/Qualification:
• Exposure to cloud computing platforms (e.g. AWS)
• Knowledge of Python
• Exposure to Physical IP development and verification flows, especially Characterization and/or circuit simulations
• Experience with industry standard EDA tools for Physical IP design is preferred