Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
As a Senior Staff EDA Software Validation Engineer at Arteris, you will have opportunity to be part of a validation team with leading-edge Electronic Design Automation expertise and you will work on the most advanced SoC assembly and Hardware/Software interface flows.
You will join a proven-successful company, and be able to influence development environment, architecture, verification, and everything in-between.
- Contribute to the functional specification of Arteris SoC integration automation products in collaboration with the Product Owner.
- Qualify the expected inputs and outputs (RTL, documentation, etc.) of our software using various CAD tools (simulators, formal proof, etc…).
- Set up the test examples, reference files and scripts (Python, Tcl, Java) allowing the automated execution of the test suite.
- Define test plans in collaboration with the Product Owner and software development/QA teams.
- Create and participate to comprehensive test campaigns.
- Identify and implement tests to be automated in the QA validation phase.
- Validate the graphical interface and APIs used by our customers.
- Maintain and enhance tests in the continuous integration flow, improve metrics, and increase automation.
- Identify and setup automation frameworks for new tests or new types of tests.
- Maintain our internal libraries (Python modules, Java plugins) for automated tests.
- Help improve and refine processes, methodologies, and metrics.
Experience and Qualifications
- 10+ years of industry experience as semiconductor CAD flow developer (Electronic Design Automation) and/or SoC design/verification engineer.
- Demonstrated experience designing and building software frameworks to assemble and verify complex System-on-Chips.
- Understanding of Hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, Tcl, SystemVerilog), able to run on any available RTL simulator (Cadence, Synopsys, Siemens).
- Knowledge of XML IP-XACT standard.
- Proficient in scripting languages (Tcl/Python) development and with GIT version control.
- Strong written and verbal communication skills in both French and English (native or CEFR C2 level in both languages)
- Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
- Experience as QA engineer in software validation under agile methodology and in API test automation
- Eclipse RCP
- ISTQB certified
- Knowledge of Squish/Cucumber
- Knowledge of TDD, BDD approaches and tools
- Understanding of CI/CD (Jenkins…)
- Experience in Java development and JUnit unit tests
- Master degree in EE (Electrical Engineering) or CS (Computer Science), PhD is a plus
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
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To view the job application please visit www.arteris.com.