Senior SRAM Designer

This position is not currently open however, we are posting for future positions that range from Junior to Senior levels for our San Jose Design Center.

Overview of Role

We are seeking a talented and motivated Senior SRAM Designer to join our team. As a Senior SRAM Designer, you will have the opportunity to work with TSMC’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. Join us in the San Jose Design Office and be part of the team that pushes the boundaries of what’s possible in the world of semiconductor manufacturing.

You will report to the Director of Memory Design Team in San Jose, California. We are currently operating in a hybrid work schedule with 4 days in office.

Responsibilities:

• Your designs will significantly impact the SoC design in the products of our customers.
• You will play a strategic role in collaborating with all fields to deliver functional products to customers quickly.
• Implement custom digital circuits for SRAM design and collaborate with an exceptional logic/architecture team to formulate design specifications.
• Hands-on design of SRAM/DRAM/Non-Volatile memory circuits & compiler timing/power characterization, netlist/layout tiling, IR/EM flow.
• Supervision of layout, compiler coding. Supervision and interpretation of testing results.
• SRAM Compiler verification/QC.
• You will primarily be a technical contributor, be part of a design R&D team and frequent interaction with Headquarters in Hsinchu, Taiwan.
• Individual contributor, need to be hands-on for all the compiler related work, not limited to circuit design only.

Minimum Requirements:

• Master’s degree in Electrical/Computer Engineering with 5+ years of related work experience; Bachelor’s degree in Electrical/Computer Engineering with 7+ years of related work experience
• In-depth knowledge with SRAM compiler development, Cadence, and Synopsys circuit design environment
• Experienced in TSMC N10 or below advanced technology circuit design & layout
• Expertise in Perl/Shell/TCL/Python language programming

Preferred Requirements:

• Exposure to TSMC N5 and below technology
• Advanced static timing analysis and sign-off
• Track record in multi-million gate design production tapeouts
• Must have good teamwork attitude and be able to work under pressure

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology