- BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)
- Worked on SoC level testbench and verification environment
- Testbench architecture, coding and good understanding of design issues in RTL
- Testbench generation, test vector creation, simulations, gate level simulations
- Hands-on with System Verilog and Assertion-based verification methodology
- At least 3 years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
- Should be able to work independently and able to guide others
- The role requires this person to be the point of contact for handling and resolving technical queries for other engineers in the team.
- Committed and passionate about technical work.
- Knowledge of RTL coding styles
- Low power verification (UPF/CPF) would be an added plus
- Experience on System C would be an added plus
- Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
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