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Senior SERDES RTL Design Engineer

Senior SERDES RTL Design Engineer
by Admin on 03-30-2022 at 3:20 pm

  • Full Time
  • Sunnyvale, CA
  • Applications have closed

Analog Bits

In this position you will play a key technical leadership role in developing and verifying PCS RTL for low power, high-speed, Fin-FET SERDES macro to be used in numerous products from high performance data center SoCs to low power consumer SoCs. You will join a highly collaborative team, and your success will have a significant impact on our products.

Candidate should have an interest in all the “Key Qualifications” listed, and significant experience in some of them.

Key Qualifications:

  • 5+ years of SERDES PCS and PMA RTL development experience
  • Expertise in SERDES protocols and PCS architecture such as PCIe, SATA, SAS, Ethernet
  • Experience in PHY-level protocol test suite development and integration with link layer controllers
  • Experience in high speed FPGA RTL porting, IO mapping, synthesis, timing closure
  • Verilog/Verilog-A/System Verilog, functional verification skills
  • Skills in writing and maintaining python code as lab test bench GUI and for test automation
  • Knowledgeable in advanced RTL digital design methodology
  • Working experience with Lint, CDC, Synthesis/P&R/STA, CTS, Xilinx FPGA compiler tools
  • Excellent team player and clear communicator
  • Ability and desire to lead while providing technical guidance

Description:

  • Contribute to the development and verification of advanced SERDES PCS logic, including clock domains crossing, calibration logic, equalization, adaptation, auto-negotiation, BER eye monitor, etc
  • Develop micro-architecture and test-chip/test-system specifications
  • Develop Verilog test benches, diagnostics, and product test flow procedures
  • Work closely with the PMA design team
  • Document the design for internal and external purposes, including maintaining PHY user guides
  • Interface with customers and assist in integrating the Serdes IP
  • Participate in all test chip and bring up activities
  • Help improve RTL design and verification methodology
  • Schedule and track the RTL development process. Provide regular status updates.

Education:

  • BS required / MS or PhD preferred in electrical engineering or related field
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