Senior RTL Designer
Education
- BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)
Key Responsibilities
- Able to understand block guides, create FSM from the description.
- Should be able to understand micro level architecture
- Develop RTL blocks from scratch and reach a point of synthesis clearance.
- Develop and execution of system use case scenarios
- Work on clock domain crossing will add more in skill-set
- Excellent team player & can guide juniors also
Knowledge/Skills
- Excellent digital skill set
- Logic development
- Good experience in Verilog & RTL coding
- Synthesys, lintin & CDC tools
- Working on NoC will add more in skills
- Protocol knowledge – AXI/ AHB/ APB/ Tilelink
The Data Crisis is Unfolding – Are We Ready?