Senior Principal Analog IC Design Engineer

The Sr. Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Candidate’s background should include a minimum of 10 years of experience in CMOS SerDes or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
• Cadence tool experience, lab test experience, and design experience at >10Gbps and in <40nm technologies are a plus
• BSEE [MSEE preferred]

Company Information:

Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs ,  System-On-Chip devices, IP and complete systems at lower costs and with higher quality.