Banner new 1

Senior/ Principal Analog Engineer – Clocking

Senior/ Principal Analog Engineer – Clocking
by Admin on 07-06-2022 at 1:16 pm

Website Agile Analog

As we embark on this journey of expansion, we are looking for Senior/Principal Analog IC Design Engineers to join our team to help revolutionise the way analog circuits are designed. These are exciting positions for ambitious, enthusiastic engineers with a passion for complex analog circuit design. You will have the opportunity to design various circuit blocks in a wide range of CMOS process technologies.

The primary focus will be developing Clocking and Communication interface circuits from VCOs, PLLs and XTAL oscillators to full Clock and Data Recovery applications.

You will be joining a highly experienced, proficient design team and will need to be a solid team player with a practical understanding of the IC design flow as well as having proven experience of taking designs from concept to mass production. These roles would suit someone who has both a systematic approach to circuit design and an innovative approach to problem solving.

Requirements

What we need from you:

  • A systematic, hands-on approach to circuit design
  • Experience in both defining specifications and designing to specification
  • BS/MSEE in a relevant field or equivalent industry experience
  • Experience in Clock Generation – PLL, VCO, XTAL, Clock and Data Recovery Circuits
  • Experience in one or more of the following areas
    • Data Converters
    • ADC and/or DAC, for Sigma Delta or Nyquist Rate from Audio to GS/s
  • Power Management
    • LDOs and/or SMPS
  • Analog Sensor Interfaces
    • Instrumentation
    • Low Noise
  • Experience in behavioural circuit modelling
  • Experience in all stages from Circuit and System Specification, into simulation, verification all the way to qualification
  • Good communication skills in English

Even better if you have:

  • Macro-level experience: integration, verification and tape-out
  • Programming experience: Python, linux, verilogA, verilogAMS, system verilog, C Matlab,
  • Team-lead experience
  • Packaging knowledge (CSP, BGA, etc.)
  • CMOS RF circuit design experience
  • CMOS process & design flow (CAD/PDK) knowledge
  • Knowledge of Cadence design tools and environment and also Mentor Calibre verification suite

Benefits

What we offer in return:

As well as the opportunity to really play a pivotal part in our success, :

  • A friendly, supportive and inclusive working environment
  • Professional development, technical and leadership
  • Flexible work hours to fit around your personal commitments
    • We consider individual requirements to work remotely
    • Home set up assistance provided
  • 25 days annual leave with the option to purchase additional days
  • Company share options
  • Professional society membership
  • Private health insurance (including optical and dental cover)
  • Company pension scheme matching to 8% (with a salary sacrifice option)
  • Life Assurance
  • Employee Assistance Programme – free wellbeing and health services
  • Cycle-to-work scheme

If the above role matches your experience, skills and motivations then we would love to hear from you and we can chat about our exciting plans.

Apply for job

To view the job application please visit apply.workable.com.

Share this post via: