CEVA PentaG RAN Banner SemiWiki 782x98 220928 220928 1

Senior Physical Design Engineer

Senior Physical Design Engineer
by Admin on 08-15-2022 at 4:04 pm

  • Full Time
  • India

Website Truechip

Education

  • BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)

Physical Design Engineer

  • knowledge of PD Flow from netlist to GDS  (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI)
  • Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc)
  • Should have worked extensively on XTalk/SI/EM
  • Knowledge about CTS, Clock tree methodology and clock skewing.
  • Tool specific knowledge: ICC, innovus, primetime, DC, Genus depending on the background
  • Knowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis.
  • Job would require complete ownership from netlist to GDS for blocks.
  • Should have worked on 28nm and lower technologies.

Tools : ICC or Innovus for PnR , Encounter for FloorPlan , Redhawk for IR Drop, PT/PTSI , Calibre

Activities : Physical design of Hard Macros/Partitions.  gate-level- Netlist to GDS, technologies varying from 28nm to 7nm .

PD activities involve: 
Hard Macro floorplan/IR Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS

Apply for job

To view the job application please visit www.truechip.net.

Share this post via: