Senior Hardware Design Verification Engineer

As a Senior Hardware Design Verification Engineer at Arteris, you will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up.

You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Key Responsibilities:

• Advanced UVM based test bench development and debugging
• Defining, documenting, developing and executing RTL verification test/coverage for very parametrized IPs in Python C++ and SystemVerilog language
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure

Experience Requirements / Qualifications:

• 7+ years of industry experience as a Verification Engineer
• Knowledge of Verilog or SystemVerilog.
• Knowledge of interconnect technology is a plus
• Knowledge of Cache architecture is a plus.
• Knowledge of AMBA protocols and AMBA VIP.
• Experience with C / C++ or Python or JavaScript is a plus.
• Good written and verbal communication skills in both French and English
• Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
• Proven ability to work well within a team

Education Requirements:

• Engineering Master’s Degree