Senior Hardware Design Verification Engineer

Key Responsibilities:

• Advanced UVM based test bench development and debugging
• Defining, documenting, developing and executing RTL verification test/coverage for very parametrized IPs in Python C++ and SystemVerilog language
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure

Experience Requirements / Qualifications:

• 7+ years of industry experience as a Verification Engineer
• Knowledge of Verilog or SystemVerilog.
• Knowledge of interconnect technology is a plus
• Knowledge of Cache architecture is a plus.
• Knowledge of AMBA protocols and AMBA VIP.
• Experience with C / C++ or Python or JavaScript is a plus.
• Good written and verbal communication skills in both French and English
• Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
• Proven ability to work well within a team

Education Requirements:

• Engineering Master’s Degree

Position based on Montigny-le-Bretonneux (78) – 2 remote days per week possible