Senior FPGA Design Engineer

About the Job

• Develop a thorough understanding of system-level design​
• Hardware verification of the digital module using cutting-edge FPGA
• Develop RTL code of system-level layers integrating Mixel MIPI IPs.​
• RTL Synthesis/FPGAP&R of the digital part of Mixed-Signal IPs.​
• Design and implement hardware verification activities through simulation environments and lab tests.
• Working with the validation team on the testing/characterization and prototyping of Mixel IPs.
• Support integrating Mixel solutions into customers’ platforms.

Job Requirements

• • Bachelor’s degree in Electronics Engineer Master’s Degree is a plus
  • 3-6 Years of experience in Digital Design/Verification
  • Strong knowledge of Verilog RTL design/simulation
  • Strong knowledge of FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
  • Familiarity with FPGAkits and FPGA hardware interfaces.
  • Knowledge of gate-level verification techniques ​

Desirable Qualifications and Experience:

• Familiarity with System Verilog, RTL/gate verification techniques is a plus
• Familiarity with testing equipment and validation platforms is a plus
• shell scripting/programming languages.
• Unix/Linux operating systems.