Senior Foundry Applications Engineer (Packaging Design)

Job Description:

Intel Foundry Services is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Using this model will ensure that our foundry customers’ products receive our utmost focus in terms of service, technology enablement, and capacity commitments.

We’re seeking a highly motivated, result driven, and talented engineer to join the ASE (Applications & Solutions Engineering) team within Intel Foundry ADG (Aerospace, Defense & Government) org to Support Intel’s IDM 2.0 vision. This person will work closely with Intel Foundry ADG customers on advanced packaging technologies to define, develop, and implement design tools, flows, and methodologies for system co-design, design implementation, and verification. Will serve as the technical expert on pkg design tools as well as consult on pkg design and implementation issues.

The ideal candidate should exhibit the following behavioral traits:

• Establish technical credibility, building trust and strong relationships with the customer.
• Ensure our customer successfully evaluates, adopts, and designs products with Intel process technology.
• Highly organized, analytical, and strong team player. Able to clearly synthesize complex information, lead in-depth tactical discussions and deliver results.
• Must be able to provide clear communications with customers and stakeholders.

Qualifications:

The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelors degree in Electrical/Computer Engineering or in a STEM related field of study.
• 8 + years of experience/background in Package Design and relevant EDA tools.
• Experience interfacing with customers and/or stakeholders.
• Experience analyzing customer design issues, environments, and define functional specs for EDA vendors.

Preferred Qualifications:

• Active US Government Security Clearance with a minimal of a Secret Level.
• Post Graduate degree in Electrical / Computer Engineering or in a STEM related field of study.
• Experience with EDA implementation or verification tools from either; Cadence, Synopsys or Siemens i.e.:
  • Multi-die/3DIC platform tools such as: Cadence Integrity, Synopsys 3DIC Compiler, Siemens Xpedition Substrate Integrator/Innovator 3D
  • Implementation tools such as: Cadence Virtuoso/Innovus, Allegro (Advanced Package Designer, APD/SiP), Siemens Mentor Xpedition (PCB Layout/XPD), Synopsys Fusion Compiler; and/or
  • Verification tools such as: Siemens Calibre, Synopsys ICV, or Cadence Pegasus

• Experience with design for verification and design for performance: Package Signal Integrity, Power Integrity, manufacturing, and yield.
• Experience analyzing customer design issues, environments, and define functional specs for EDA vendors.
• Experience with scripting in tcl, Python, SKILL, VBScript, etc for design flows, and efficiencies.